Thesis title: Data-centric Methodologies for Efficient High-Level Synthesis

Abstract: Field Programmable Gate Arrays (FPGAs) have emerged as a compelling platform for generating application-specific hardware, offering high performance and energy efficiency while retaining flexibility for post-deployment updates. Programming FPGAs at the Register Transfer Level (RTL) has traditionally posed significant challenges, as designers must explicitly manage hardware resources, timing, and parallelism, requiring deep expertise in digital logic and device architecture. High-Level Synthesis (HLS) mitigates many of these challenges by enabling designers to express hardware behavior using high-level languages, while the compiler automatically identifies parallelism and generates the corresponding RTL. This abstraction simplifies development, accelerates design exploration, and reduces the complexities of traditional hardware description language workflows. Despite these advantages, HLS introduces its own difficulties, as designers must carefully reason about how high-level constructs translate into hardware, particularly regarding parallelism, pipelining, and memory behavior, while the manual tuning of compiler directives combined with the slow feedback cycle of synthesis results creates a large and intricate design space, making it challenging to achieve optimal outcomes.

In this dissertation, we investigated HLS Design Space Exploration (DSE) through three interrelated perspectives, each corresponding to a critical layer of the process. At the data layer, we developed GNΩSIS, a large-scale and diverse HLS design corpus, providing a robust foundation for training and benchmarking contemporary learning-based optimization methodologies. At the modeling layer, we introduced language-level performance and resource prediction techniques that enable early-stage, accurate estimation of HLS optimization effects, significantly reducing dependence on time-intensive synthesis runs. At the optimization layer, we proposed CollectiveHLS, a rapid, knowledge-driven framework for directive selection that leverages historical design behaviors to guide exploration and generate effective optimization strategies for unseen applications. Together, these contributions constitute a comprehensive approach to HLS DSE, enhancing scalability, predictive accuracy, and practical applicability across the entire optimization workflow. Finally, to bridge the gap toward real FPGA deployments, we propose a QoS-aware FPGAaaS framework that generates Pareto-optimal hardware variants for each application and dynamically selects the most appropriate one at runtime based on available resources, thereby improving resource utilization and reducing QoS violations.

Supervisor: Sotirios Xydis

PhD Student: Aggelos Ferikoglou