We are pleased to announce that the paper entitled " An Energy-Efficient Analog Hardware Artificial Neural Network Architecture for Obesity Classification" received the 3rd place Best Paper Award in the 37th International Conference on Microelectronics (ICM), which took place in Cairo Egypt from 14-17 December 2025.

The Award-Winning paper was co-authored by Andreas Papathanasiou (PhD Student, ECE-NTUA), Anna Mylona (Diploma Student, ECE- NTUA and Researcher Archimedes/Athena RC) , Dr. Vassilis Alimisis (Collaborating Researcher, ECE-NTUA and Postdoctoral Researcher Archimedes/Athena RC) ,and Paul P. Sotiriadis (Professor, ECE-NTUA; Lead Researcher, Archimedes/ Athena RC; IEEE, AIIA & AAIA Fellow ).

ABSTRACT: This study introduces a new implementation of an artificial neural network classifier using a low-power integrated analog architecture. The proposed current-mode design utilizes compact analog circuits to implement the Rectified Linear Unit (ReLU), sigmoid and correlation functions. A Winner-Take-All (WTA) circuit generates the final decision of the classifier. These analog building blocks operate in the sub-threshold region and the overall architecture functions at sub-microWatt levels with supply rails as low as 0.6 V. The effectiveness of the classifier is evaluated on a real-world obesity classification dataset, where high classification accuracy is demonstrated with a median value of 96.31%, with an average power consumption of 994nW. The system is designed using TSMC’s 65nm CMOS technology within the Cadence IC Suite, encompassing both schematic entry and layout development. Simulation over corners and a Monte Carlo analysis accounting for mismatch and process variations are carried out to validate the reliability of the design. The postlayout results obtained are rigorously compared with both a software counterpart and findings from existing literature, thereby verifying the strong effectiveness of the proposed architecture.