ECE-NTUA Microlab received the Best Paper Award in 30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2022)
We are pleased to announce that the paper entitled “Combining Fault Tolerance Techniques and COTS SoC Accelerators for Payload Processing in Space” received the Best Paper Award in the 30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) that was held on October 3-5, 2022.
The award-winning paper was a joint publication with the National and Kapodistrian University of Athens, Department of Physics, and was co-authored by Vasileios Leon (NTUA), Elissaios Alexios Papatheofanous (NKUA), George Lentaris (NTUA), Charalampos Bezaitis (NKUA), Nikolaos Mastorakis (NTUA), Georgios Bampilis (NTUA), Dionysios Reisis (NKUA), and Dimitrios Soudris (NTUA).
The work was partially supported by research activities of the European Space Agency (ESA), the EU project EVOLVE (grant agreement 825061) and the Hellenic Foundation for Research and Innovation (PhD fellowship number 6220).
Short Abstract: The ever-increasing demand for computational power and I/O throughput in space applications is transforming the landscape of on-board computing. A variety of Commercial-Off-The-Shelf (COTS) accelerators emerges as an attractive solution for payload processing to outperform the traditional radiation-hardened devices. Towards increasing the reliability of such COTS accelerators, the current paper explores and evaluates fault-tolerance techniques for the Zynq FPGA and the Myriad VPU, which are two device families being integrated in industrial space avionics architectures/boards, such as Ubotica's CogniSat, Xiphos' Q7S, and Cobham Gaisler's GR-VPX-XCKU060. On the FPGA side, we combine techniques such as memory scrubbing, partial reconfiguration, triple modular redundancy, and watchdogs. On the VPU side, we detect and correct errors in the instruction and data memories, as well as we apply redundancy at processor level (SHAVE cores). When considering FPGA with VPU co-processing, we also develop a fault-tolerant interface between the two devices based on the CIF/LCD protocols and our custom CRC error-detecting code.