PhD thesis defense to be held on December 13, 2022, at 10:00 [B.1.14/MS Teams (hybrid)]

Picture Credit: Nikolaos Temenos

Thesis title: Stochastic Computing Architectures for Information Processing Systems

Abstract: Arithmetic operations on stochastic sequences is the basis of the unconventional technique known as Stochastic Computing (SC). Deviating from the standard binary arithmetic, SC encodes and processes the value of binary numbers in the form of stochastic sequences making arithmetic operations and highly complex functions to be realized simply using a few standard logic gates and memory elements. Along with SC’s natural robustness on soft-errors, its properties and advantages have been exploited in a plethora of fields with massive parallelism needs and small error tolerance including Neural Networks and Image Processing among many. Beyond its strong points, SC introduces an accuracy-latency trade-off impacting on the energy efficiency and hence to make the best of it, achieving low latency combined with increased computational accuracy is the primary concern.
In this dissertation novel architectures realizing essential arithmetic operations and non-linear functions in SC are presented. The internal registers they utilize make their input sequence processing deterministic, thereby improving on the SC’s accuracy-latency trade-off. To demonstrate the architectures’ properties and operation principle, they are analysed in-depth using Stochastic Finite-State Machines (SFSM) and modeled using Markov Chains (MC). In the first part of the dissertation, the operation principle of the architectures is analysed using SFSMs and modeled using MCs which allows for a better understanding of their long-term stochastic dynamics and the verification of their proper operation. The MC modeling is further extended to a general methodology enabling the analytical derivation of the SFSMs’ first and second moment statistical properties. The methodology is accompanied by overflow/underflow MC modeling, allowing to estimate the number of states that reduce bit-errors originating from the overflow/underflow occurrence, hence setting the guidelines for the selection of the register’s size. In the second part of the dissertation, the architectures are compared extensively with existing ones in the SC literature in computational accuracy and hardware resources, including area, power and energy consumption as well as in the benefits they introduce in the overall design flow. The efficacy of the architectures is demonstrated with their use as building blocks in the realization of several DSP tasks, including convolution, noise reduction and image down-sampling filters as well as Neural Networks. The results of the architectures’ performance in computational accuracy and hardware resources are compared to those achieved using standard binary computing methods highlighting their advantages.

Supervisor: Professor P. - P. Sotiriadis

PhD Student: Nikolaos Temenos