Research by Prof. Paul P. Sotiriadis's Group Highlighted in IEEE Transactions on VLSI Systems
We are pleased to announce the publication of the paper titled "Power-Efficient Analog Hardware Architecture of the Learning Vector Quantization Algorithm for Brain Tumor Classification" featured in the November 2024 issue of IEEE Transactions on VLSI Systems, one of IEEE's leading journals. This work forms part of Dr. Vassilis Alimisis's Ph.D. thesis, supervised by Professor Paul P. Sotiriadis.
The paper was co-authored by Vassilis Alimisis (Postdoctoral Researcher, ECE-NTUA and Researcher Archimedes/Athena RC), Emmanouil Anastasios Serlis (Graduate, ECE-NTUA), Andreas Papathanasiou (Graduate, ECE-NTUA), Nikolaos P. Eleftheriou (Graduate, ECE-NTUA), and Paul P. Sotiriadis (Professor, ECE-NTUA; Lead Researcher, Archimedes/Athena RC; IEEE Fellow).
ABSTRACT: This study introduces a design methodology pertaining to analog hardware architecture for the implementation of the learning vector quantization (LVQ) algorithm. It consists of three main approaches that are separated based on the distance calculation circuit (DCC) and, more specifically; Euclidean distance, Sigmoid function, and Squarer circuits. The main building blocks of each approach are the DCC and the current comparator (CC). The operational principles of the architecture are extensively elucidated and put into practice through a power-efficient configuration (operating less than 650 nW) within a low-voltage setup (0.6 V). Each specific implementation is tested on a brain tumor classification task achieving more than 96.00% classification accuracy. The designs are realized using a 90-nm CMOS process and developed utilizing the Cadence IC Suite for both schematic and physical design. Through a comparative analysis of post-layout simulation outcomes with an equivalent software-based classifier and related works, the accuracy of the applied modeling and design methodologies is validated.