PhD Thesis Final Defense to be held on June 12, 2019, at 13:30
Photo credit: Konstantinos Maragos
The examination is open to anyone who wishes to attend (New ECE-NTUA building, Conference Room).
Thesis Title: Design Methodologies, Frameworks and Implementations on Reconfigurable Devices for Timing and Energy Optimizations
Abstract: The fabrication of more advanced chips has become increasingly challenging and economically inefficient as transistors reach the atomic scale. Major reliability issues including process variability, voltage drop effects and thermal dissipation are becoming even more pronounced in new technology nodes. To cope with the aforementioned issues and provide acceptable solutions, the chip vendors impose global and conservative guard-bands in the operation of their manufactured chips. Such pessimistic strategy, however, does not utilize the actual performance capabilities of the individual chips and does not adapt to those operating conditions (e.g., \textit{IR}-drop) that strongly depend upon the individual characteristics of an application. Therefore, significant performance is lost, either in terms of frequency or power consumption. In the current research work, we focus on FPGA chips and we aim at delivering adaptive solutions with respect to the quality of the underlying silicon and the specifics of the application executed on the chip. We propose a methodology for the characterization of the actual performance capabilities of present-day commercial FPGA chips subjected to process variations. The methodology bases on the generation of variability maps for the evaluation of performance variation across the FPGA fabric. Capitalizing on the generated variability maps and the potential gains of exploiting the conservative guard-bands, we introduce a framework to enhance the performance of the FPGAs. The framework is based on variability maps and frequency and voltage scaling methods. The former serves the purpose of mapping a given design to most efficient region (intra-die) and device (inter-die). The latter, is used to calibrate the FPGA operation to the optimal operating point with respect to the user specifications. With our experimental setup and a set of 28nm FPGAs and realistic benchmarks, we exhibit solutions which can even double the maximum performance of an application when compared to the nominal STA estimations of industrial EDA tools. In addition to the above framework, we introduce an alternative method targeting the energy efficiency improvement of commercial FPGAs providing increased self-sufficiency. The proposed method is based on a reliable sensing scheme to regulate the voltage by holistically considering all process, voltage and temperature variations during the operation of the FPGA. A key characteristic of this method is that it can be integrated as a ready-to-use IP in any user-design. Based on real-world DSP benchmarks, the experimental results exhibit significant power savings while maintaining the functional integrity and nominal timing performance.
Supervisor: Dimitrios Soudris, Professor
PhD student: Konstantinos Maragos